Optimizing Stack Frame Layout for Embedded Systems

Johnny Burlin
IAR Systems AB

Many modern embedded processors have powerful, yet restricted addressing modes, they might for example allow indirect addressing but with a small offset. The small offset creates a partitioning of the activation frame into two parts, a fast part the can be accessed directly and a slow part that require arithmetic operations on the stack pointer before the activation frame can be accessed. We propose a greedy algorithm that places frequently accessed variables on the fast activation frame to reduce code size and uses the liveness properties of variables to let variables that not are live at the same time share space on the activation frame and thereby save space. By minimizing the number of variables on the slow part of the activation frame, it is possible to reduce both stack size, code size and execution time. We present experimental results that show that our method uses less stack and generates less code than the algorithm of a leading industrial compiler.

ASTEC seminar
January 16, 2001

Place: Information technology, Uppsala University
Room: 1510
Time: 15.00-16.00 (+ discussions)
Please note time

Room 1510 is in Building 1, Floor 5, room 10 (in the southern part of the building).

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There will be an extended period for discussions after the seminar.

Speakers are encouraged to give an short (5 min) introduction to the subject at the begining of the talk.
Listeners are excused if they have to leave after 16.00.

Updated 15-Jan-2001 14:41 by Roland Grönroos
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