Optimized Instruction Set Simulator Model
Flexible ASIC (FlexASIC) is a concept for a System-on-Chip (SoC)
architecture developed at the Ericsson Microelectronics Design Centre
in Kista, Stockholm. It allows integration of several customized DSP
cores on one SoC ASIC. The processors are assembled from a library of
general core building blocks that together with one or several tailor-
made hardware building blocks, forms the customized DSP core. The
processors are supported by several software development tools
including a C compiler, an assembler, a linker and a simulator with
debugging capabilities. This thesis work focus on the simulator.
The present simulator allows cycle accurate simulation and debugging
of a FlexASIC DSP core program. The property of cycle accuracy means
that a program instruction taking n clock cycles to execute on the
actual DSP hardware, will be reported as taking n clock cycles when
simulated. In its current form, the simulator is in the order of
20000 times slower than the target processor. This often means many
hours of simulation.
The scope of this thesis work has been to investigate if it is
possible to construct a new simulator model which is significantly
faster than the present one by removing the constraint of cycle
accuracy. This new simulator would not replace the present one, but
rather be a complementary model. This thesis work also includes a
partial implementation of a new model.
Tomas has worked with
optimizing a DSP simulator at Ericsson, and is examined by Jakob
Engblom of the ASTEC/WCET project.
Do not miss the seminar by Martin Carlsson starting at 13.15 in the same room.
Place: Information technology, Uppsala University
Time: 14.15-15.00 (+ discussions)
Room 6003 is in building 6, floor 1, room "143 Seminarierum" on construction drawing, enter via the MIC-aula entree.
Everyone is welcome !
Updated 05-Mar-2002 12:01 by Roland Grönroos
e-mail: info -at- astec.uu.se