Abstract
The quest for quantitative performance analysis in computer architecture research and design led to many research papers based on the commercially important DSS and OLTP database applications. Today's middleware, and in particular application servers, are rapidly gaining popularity as a new workload for commercial multiprocessor servers. Therefore, it is important to expand architecture studies into this area. SPEC has recognized the importance of application servers and Java-Based middleware with its recent adoption of SPECjAppServer2001, formerly ECperf, as one of its benchmarks. In this paper, we present a detailed characterization of the memory system behavior of ECperf running on both commercial server hardware and in a simulated environment. We find that the working sets of ECperf fit in a reasonably sized L2 cache, but that the miss rate is very sensitive to associativity. Furthermore, many of the L2 misses in ECperf are satisfied by data from the cache of a neighboring processor. Based on these findings, we conclude that ECperf is an excellent candidate for shared-cache memory systems, even when the total cache size is limited.

Appears in Proceedings of the 2nd Annual Workshop on Memory Performance Issues (WMPI 2002), held in conjunction with the 29th International Symposium on Computer Architecture (ISCA29), Anchorage, Alaska, USA, May 2002.

Contact: martink@docs.uu.se

This talk will take 25 min the seminar will continue with
RH Lock: A Scalable Hierarchical Spin Lock
by Zoran Radovic

ASTEC seminar
May 16, 2002

Place: Information technology, Uppsala University
Room: 1146
Time: 14.15-15.00 (+ discussions)

Room 1146 is in building 1, floor 1, room 46 (in the northern part of the building).

There will be an extended period for discussions after the seminar in the coffe room on floor 4.

Speakers are encouraged to give an short (5 min) introduction to the subject at the begining of the talk.
Listeners are excused if they have to leave after 15.00.