WCET Analysis for Instruction Level Parallel Processors
Seoul National University
Techniques to derive the worst case execution times (WCETs) of tasks in real-time systems have evolved to consider key components of RISC processors such as pipelining and caching. As WCET analysis community expected, RISC processors are increasingly used in embedded/real-time systems because the applications of embedded/real-time systems have been gradually diversified. We also expect that, in near future, instruction level parallel (ILP) processors such as superscalar or VLIW processors will be used in embedded/real-time systems as demanded performance significantly increases. For the ILP processors, the assumptions made in existing WCET analysis techniques for simple RISC processors may not hold in the following aspects: The dynamic execution behaviors of instructions in ILP processors will be more heavily dependent on the executions of surrounding instructions than in simple RISC processors. Furthermore, advanced compiler optimizations (especially used in VLIW processors) will complicate making correspondence between high-level program structures and low-level ones.
This talk will give issues in WCET analysis for ILP processors; The issues include accurate modeling of the components in ILP processors such as multiple-issue capability and branch prediction and reflecting the aggressive optimizations of compilers in WCET analysis. This talk will introduce an approach based on a hierarchical source-level WCET analysis technique called extended timing schema (ETS) for ILP processors proposed by real-time research team at Seoul National University. This work aims at accurately modeling the architectural features of ILP processors and as the first step, we assume a simple in-order superscalar processor model and focus on accurate modeling of multiple-issue capability of superscalar processors. Finally, in this talk, future work to put the proposed WCET analysis techniques into practice will be given.