Validation of cycle-accurate CPU simulators against real hardware
Melody Interactive Solutions AB
Knowing the Worst-Case Execution Time (WCET) of a program is necessary when
designing and verifying real-time systems. Using static analysis tools is a
safe way to obtain WCET estimates. However, the analysis will only yield
correct results if the tools are correct. Most WCET tools depend on some
software model (or simulator) of the target system to obtain timing
estimates. In order to guarantee safe WCET estimates, the timing model must
We have done a case study in validating a cycle-accurate CPU simulator
against the real hardware CPU. We have used a methodology based on black-box
tests that relies on hardware analysis for test-case generation. By
systematic analysis of the CPU architecture, we generate a set of test cases
which are run in both the simulator and on the hardware. The simulator is
validated by comparing the resulting execution times.
The method aims at both determining the accuracy of the simulator and to
pinpoint simulator errors, allowing timing errors to be corrected. In our
case study, we managed to reduce the average timing error for a NEC V850E
simulator from 11,2 % to 1,3 % for a set of benchmark programs. Our
methodology should be easy to apply to similar architectures.
Place: Information technology, Uppsala University
Room 1510 is in Building 1, Floor 5, room 10
(in the southern part of the building).
Help on how get here and
MIC campus drawing.
There will be an extended period for discussions after the seminar.
Speakers are encouraged to give an short (5 min) introduction to the subject at the begining of the talk.
Listeners are excused if they have to leave after 15.00.
Updated 18-Dec-2000 08:35 by Roland Grönroos
e-mail: info -at- astec.uu.se