ASTEC seminars

Unless othervise stated are the seminars held in seminarroom 1406 at 13.15 - 14.00.
Room 1406 is in Building 1, Floor 4, room 06 (in the southern part of the building).
Help on how get here and MIC campus drawing.

There will be an extended period for discissions after the seminar
nourished by buns and coffe.

Speakers are encouraged to
- give an short (5 min) introduction to the subject at the begining of the talk.
- keep the time (listeners are excused if they have to leave at 14.00).

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Timing Analysis for Modern Architectures

Sang Lyul Min
Dept. of Computer Systems
Uppsala University
16 february 1999

In this talk, I will describe an extension of the timing schema to analyze the timing effects of RISC's pipelined execution and cache memory. In the extension, concatenation and pruning operations on what we call worst case timing abstractions (WCTAs) replace the add and max operations on time-bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. I will also present a technique for analyzing cache-related preemption delays of tasks that cause unpredictable variation in task execution time in the context of fixed-priority preemptive scheduling. The technique consists of two steps. The first step performs a per-task analysis to estimate cache-related preemption cost for each execution point in a given task. The second step computes the worst case response time of each task using a response time equation and a linear programming technique. I will also describe enhancements to the technique along with results from our simulation study that compares the proposed technique with previous ones.

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Updated 1999-02-04
Roland Grönroos