Past seminars

March 7, Model-based Test-Case Selection and Generation for Real-Time Systems, Licenciate seminar by Anders Hessel

2005

Nov 3, Extending Optimising Compilation to Support Worst-Case Execution Time Analysis, Raimund Kirner, TU Wien.
April 14, Concrete Model Checking with Abstract Matching and Refinement Radek Pelanek, Faculty of Informatics, Masaryk University Brno.
Jan 20, Modeling Real-time Systems, Joseph Sifakis, Verimag, Grenoble, France

2004

May 25, Programming Smart Phones: Practical Experiences
Christoffer Eriksson and Daniel Guldbrandsen
May 11, Constraint-Based Mode Analysis of Mercury Programs
Zoltan Somogyi
Dept of Computer Science and Software Enginneering, University of Melbourne, Austalia.
March 8, Undecidability of Weak Bisimulation Equivalence for 1-Counter Processes
PD Dr. Richard Mayr, Albert-Ludwigs-University Freiburg
February 11, Technique of so called DD-functions in deciding bisimilarity
Petr Jancar, Techn. Univ. Ostrava, Czechia
Adaptive Pattern Matching on Binary Data
Per Gustafsson, Information technology, Uppsala University

2003

Three seminars November 25, 2003
- 10.15 - 10.55, In-vehicle electronic and communication infrastructure by Gabriel Leen
- 11.00 - 11.25, Time-Triggered Controller Area Network, an overview by Gabriel Leen
- 11.30 - 12.00, A Demonstration System for a New Time-Triggered Sensor Network, Based on IEEE 1451 by Paula Doyle
September 24, Profit Driven Optimizations
Mary Lou Soffa, Department of Computer Science, University of Pittsburgh
April 1, 2003, From Simulation to Bisimulation and Back
Richard Mayr, Albert-Ludwigs-University Freiburg, Germany
March 12, 2003 The ASTEC Cluster on Distributed Embedded Real-Time Systems (CODER) give an afternoon seminarseries.
13.15: Introduction to the CODER cluster. Jakob Engblom, Uppsala University.
13.30: Register Allocation for Embedded Architectures. Sven-Olof Nyström, Uppsala University.
14.20: Program Flow Analysis for Worst-Case Execution Time Analysis. Jan Gustafsson, Mälardalens Högskola
15.10: Simulation of a Distributed Real-Time System Anders Möller, CC-systems.

2002

November 14, ASTEC, Half-Day-Seminar The Erlang/HiPE resluts are presented.
October 21, Compilation of Floating Point Arithmetic in the High Performance Erlang Compiler
Tobias Lindahl, Uppsala University, ASTEC Master Thesis Presentation
October 1, Expressive Power of Temporal Logics
Alexander Rabinovich, Tel Aviv University (Israel)
October 2, Native code compilation of Erlang's bit syntax
Per Gustafsson, Uppsala University, ASTEC Master Thesis Presentation
September 23, On the Complexity of Bisimulation Equivalence for Pushdown Automata
Richard Mayr, University Freiburg, Germany
September 17, A logic of probability with decidable model-checking
Alexander Rabinovich, Tel-Aviv University, Israel
Sept 3, Algorithmic Analysis of Polygonal Hybrid Systems
Gerardo Schneider
June 5, Towards Automatic Synthesis of Statistical Data Analysis Programs
Bernd Fischer, Automated Software Engineering Group USRA/RIACS, NASA Ames Research Center, California, USA
June 6, Model Checking Birth and Death
Joost-Pieter Katoen, University of Twente, Holland
May 16, Double seminar
1. Memory Characterization of the ECperf Benchmark
Martin Karlsson, Department of Information Technology, Uppsala University
2. RH Lock: A Scalable Hierarchical Spin Lock
Zoran Radovic, Department of Information Technology, Uppsala University
May 14, Timing analysis of an SDL subset in Uppaal.
Anders Hessel, Department of Information Technology, Uppsala University
May 13, Semantic Web and Formal Specifications
DONG, Jin Song, School of Computing, National University of Singapore
April 8, A Process-Algebra-Like Framework for Modelling Hybrid Systems
Michael Baldamus, Karlsruhe
April 2, Exploring Alternative Memory Architectures for Erlang: Implementation and Performance Evaluation
Jesper Wilhelmsson, Uppsala University, Information technology and ASTEC
March 26, Automated analysis of dynamic web services
Jonas Boustedt, Högskolan i Gävle and ASTEC
March 19, Worst Case Execution Time Analysis, Case Study on Interrupt Latency for the OSE Real-Time Operating System
Martin Carlsson, KTH
March 19, Optimized Instruction Set Simulator Model
Tomas Östlund, Datavetenskapligt program, Uppsala University
Jan 15, 2002,The design and implementation of a soft-typing system for Erlang
Sven-Olof Nyström, ASTEC, Uppsala University

2001

Dec 11, 2001, Semantics-based models for confidentiality of multi-threaded programs
Andrei Sabelfeld, Chalmers University of Technology
Dec 4, Efficient Longest Executable Path Search for Programs with Complex Flows and Pipeline Effects.
Andreas Ermedahl, Uppsala University
Nov 29, What is a proof engine?
Mats Boman, Prover Technology
Nov 27, Using (Timed) Petri Nets for Verification of Parameterized (Timed) Systems
Parosh Abdulla, Uppsala University
Nov 23, Segment Order Preserving and Generational Garbage Collection for Prolog
Kostis Sagonas, Uppsala University
Nov 12, Storage Allocation for Embedded Processors.
Jan Sjödin and Carl von Platen.
Uppsala University and IAR Systems AB
Oct 30,Timed Automata with Asynchronous Processes: Schedulability and Decidability
Wang Yi, Tobias Amnell, Elena Fersman, Paul Pettersson
ASTEC , Uppsala University
Automatic Code Generation for Timed Automata
Tobias Amnell, Elena Fersman, Paul Pettersson, Wang Yi
ASTEC , Uppsala University
Sept 18,Time accurate simulation
Magnus Nilsson, CC Systems AB
Sept 04, Combining Specification Techniques for Processes, Data and Time
Prof. Dr. Ernst-Rüdiger Olderog University of Oldenburg
Sept 04, Adapting Gurvich-Karzanov-Khachiyan's Algorithm for Parity Games: Implementation and Experimentation
EMMANUEL BEFFARA (Ecole Normale Superieure de Lyon, France)
presented the results of his exjobb project (advisor: Sergei Vorobyov, IT/UU)
Aug 28, Extracting the processes structure of Erlang applications
Jan Nyström, Department of Computer Systems, Uppsala University
June 12, First steps towards the formal verification of a distributed Video on Demand server
Juanjo Sanchez Penas, University of Corunna, (Galicia, Spain) Place: Ericsson, CSLab, conference room,
June 6, RASCAL -- Timestamp-Based Selective Cache Allocation
Martin Karlsson
Information Technology, Uppsala Architecture Research Team, Uppsala University.
May 29, K. Rustan M. Leino, ESC/Java and Houdini, Compaq Systems Research Center
Palo Alto, U.S.A.
April 10, Paul Pettersson, Uppsala University
Guiding and Cost-Optimality in UPPAAL
March 22, Henrik Leerberg, IAR Systems A/S, Denmark.
UML Statecharts and IAR visualSTATE
March 20, Henning Makholm, Datalogisk Institut, Dept. of Computer Science, University of Copenhagen
Region-based memory management for Prolog
March 13, Lars Albertsson, Computer and Network Architectures Laboratory, Swedish Institute of Computer Science
Simulation-Based Debugging and Profiling of Soft Real-Time Applications
March 6, Saddek Bensalem, Uppsala University
Incremental Verification by Abstraction
February 27, Jens Knoop, University of Dortmund, Germany
Parallel Optimization of Parallel Programs
February 27, Antonin Kucera, Masaryk University Brno
Decidability and Complexity Issues for One-Counter Machines
January 30, Lars-åke Fredlund, ASTEC, SICS
A formal semantics for a subset of Erlang
January 16, Johnny Burlin, ASTEC, IAR Systems AB
Optimizing Stack Frame Layout for Embedded Systems
January 12, 2001, Prof Melvin Fitting, Department of Mathematics and Computer Science, Lehman College, New York.
Modal logics between propositional and first-order

2000

December 19, 2000, Sven Montan, ASTEC, IAR Present adress: Melody Interactive Solutions AB
Validation of cycle-accurate CPU simulators against real hardware
November 29, Sven-Olof Nyström, PLACE: "Nya Telegrafen" Room, KTH/IT
The design and implementation of a soft-typing system for Erlang
November 28, 2000Jan Lindblad, Enea OSE Systems AB
Runtime software upgrades
November 24, Johan Runeson, ASTEC, UU and IAR Systems AB
Optimizing Code Size Through Procedural Abstraction
November 21, Nerina Bermudo and Xavier Vera, ASTEC, MDH
A Fast and Accurate Approach to Analyze Cache Memory Behavior
November 14, Gunnar Övergaard, KTH
Formal Specification of Object-Oriented Meta-Modelling
November 7, Clara Benac Earle, ASTEC, Ericsson Utvecklings AB.
VERIFICATION OF ERLANG PROGRAMS USING EVT
October 17 2000,Oliver Möller, University of Aarhus
Hierarchical partitioning (really) helps - from flat structures to hierarchies
October 2, 2000, Richard O'Keefe, Virtual Subnodes for Erlang
September 29 2000, Bart Demoen (K.U. Leuven, Belgium),
Term representations, instruction compression and argument passing in the WAM.
September 26, 2000, Mikro-symposium with ASTEC scientific evaluators

David Whalley, Florida State University, USA
Using Interactive Compilation to Improve the Development of Embedded Systems Applications
Joseph Sifakis, VERIMAG, France
A methodology for the construction of scheduled systems

September 5, 2000, Bengt Jonsson, ASTEC, Uppsala University
REGULAR MODEL CHECKING
August 17, 2000, Gerardo Padilla, ASTEC Uppsala University
An Execution Semantics for MSC2000
June 20, 2000, Cosimo Laneve, Department of Computer Science - University of Bologna
A Type System for JVM Threads
June 7, 2000. Ahmed Bouajjani, Liafa - University of Paris 7
Symbolic Techniques for Parametric Reasoning about Counter and Clock Systems
May 30, 2000, Dr Jian Zhang, Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences
Search for Finite Models of First-order Theories: Techniques and Applications
May 2, 2000, Jan Gustafsson, Uppsala and Mälardalen Universities
Worst Case Execution Time Analysis Using Abstract Interpretation
April 19, 2000, Shahar Maoz, Tel Aviv University
present a joint work with Alex Rabinovich Why Are There So Many Temporal Logics Over Trees?
April 4, 2000, Jakob Engblom, IAR Systems AB and Uppsala University
New Tradeoffs in an Old Trade GP1000, Crusoe, ARC, The seminar slides
March 27, 2000 Margus Veanes, Microsoft Research
Abstract State Machines in Software Development
March 14, 2000 SungSoo Lim, Seoul National University.
WCET Analysis for Instruction Level Parallel Processors
March 7, 2000, Julien d'Orso, Uppsala University
The FixIt Model Checking Tool
February 29, 2000Marcus Nilssson, Uppsala University
Transitive Closures of Regular Relations for Verifying Infinite-State Systems
February 17, 2000 Daniel Löf, Uppsala University
Tools for Automated Testing of WWW applications
February 15, 2000 Thomas Noll, KTH
Truth - A Verification Tool for Distributed Systems
February 8, 2000 Peter Magnusson, Virtutech
Virtutech Simics - a Virtual Server
feb 1, 2000, Bengt Jonsson, Introduction to and Overview of the SPIN Model Checker.

1999

November 1, 1999, Erik Johansson, ASTEC licenciate seminar, Performance Measurements and Process Optimization for Erlang.
October 20, 1999 , Hampus Delin, Bilda företag i samband med Venture Cup tävlingen.
September 29, 1999. Dr. Iain Bate, University of York, UK. Scheduling and Timing Analysis for Safety Critical Systems
June 1, 1999, Kim G. Larsen, BRICS and Department of Computer Science, Aalborg University, Denmark. UPPAAL 1995 - 2000
April 21 1999, 13.15 in 1245, Kazuhiko Kato, University of Tsukuba, Japan.
An Approach to Mobile Software Robots for the WWW
April 14 1999, Pierre Flener, Using Schemas to Reduce Inference in Automated Software Engineering
26 march 1999 - Thomas Vesterlund and Bogdan Bereza, ENEA Test, ENEA automatic testing.
12 march 1999 - Bengt Asker, At last! Software has grown up.
23 february 1999 - Jakob Engblom, Differences Between SpecInt95 and Real Embedded Programs

16 february 1999 - Sang Lyul Min, "Timing Analysis for Modern Architectures"

1996-1998

seminar 9 mars 98
3rd seminar: 16 October 1996
2nd seminar: 12 June 1996
1st seminar: 12 March 1996

Updated 28-Apr-2006 08:58 by Roland Grönroos
e-mail: info -at- astec.uu.se Location: http://www.astec.uu.se/Seminars/past-sem.shtml

Uppsala University

Department of Information Technology

ASTEC